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On Wed, 20 Jul 2016 10:07:12 +0100
"Daniel P. Berrange" <berrange at redhat.com> wrote:

Hey Daniel, thanks for the feedback.

> > Thoughts?
> 
> I'd suggest you'll increase your chances of success with nova design
> approval if you focus on implementing a really simple usage scheme for
> FPGA as the first step in Nova.

This. Maybe I'm wrong, but for me the minimal use case for FPGA would
be ability to schedule VM which need certain accelerator from multiple
potential ones on available FPGA/fixed slot. How insane does it sound?

Providing fixed, prepared earlier by DC administrator accelerator
resource, doesn't bring much value, beyond what we already have in
Nova, since PCI/SR-IOV passthrough might be used for accelerators,
which expose their functionality via VF.

> All the threads I've see go well off into the weeds about trying to 
> solve everybody's niche/edge cases  perfectly and as a result get 
> very complicated.

The topic is complicated :)

> For both NUMA and PCI dev assignment we got initial success by cutting
> back scope and focusing on the doing the minimum possible to satisfy
> the 90% common use cases, and ignoring the less common 10% initially.
> Yes this is not optimal, but it is good enough to keep most people
> happy without introducing massive complexity into the designs & impl.
> 
> For FPGA, I'd like to see an initial proposal that assumed the FPGA
> is pre-programmed & pre-divided into a fixed number of slots and simply
> deal with this. This is similar to how we dealt with PCI SR-IOV initially
> where we assumed the dev is in VF-mode only. Only later did we start to
> add cleverness around switching VF vs PF mode. For FPGA I think any kind
> of dynamic re-allocation/re-configuration is better done as a stage 2

Okay. That sounds reasonable.

-- 
Cheers,
Roman Dobosz