Open Stack

On Tue, 19 Jul 2016 15:51:26 -0700
Ed Leafe <ed at leafe.com> wrote:

> >> Why would a VM program the slot? Wouldn’t it usually be at the
> >> host level?
> >
> > Are there no cases where a VM might want to download a proprietary
> > program into an FPGA?
>
> That doesn’t sound right to me, but maybe I’m just not that familiar
> with FPGA specifics. In general, VMs don’t control their hosts. It
> would also bring up some complications, such as what should happen
> when you delete that VM: does the FPGA have to be reset to its
> original state?

Technically, it is not necessary to "erase" the FPGA. It might be
untouched, and in resource tracker it would be figured as free, so
than it can be programmed another accelerator, or passed to another VM
if needed. It may be also zeroed (programmed with empty IP) by
external entity which might be preferred option.

> >> I’m still not seeing the need for nesting. If you have a single
> >> FPGA with 8 slots, when you program the slots with accelerators,
> >> you now have 8 consumable resources. The fact that they came from
> >> a particular FPGA unit doesn’t seem relevant from a scheduling
> >> perspective.
> >
> > If you want to be able to provide an FPGA as either a whole
> > un-programmed FPGA or as pre-programmed resources, you'd
> > presumably need to know which whole FPGAs are available and which
> > have been fractionally allocated, no?
>
> An unprogrammed FPGA is a particular resource class. When you
> program it, you are removing one of that class and creating one or
> more of a new resource class (e.g., an encryption accelerator
> program). There isn’t a need to nest anything.

Although you have to track *where* you can schedule potential
accelerator, isn't it? Certain type of IP will need proper slot, so it
also have to be tracked. Nesting isn't necessary, but might be helpful
to manage the state of your resources.

> > I agree that if you are only going to have the host program the
> > FPGA and then make the resources available then the scheduler
> > doesn't need to know about whole FPGAs.
>
> That was where we left the discussion in Austin, so that was my
> assumption.

… as the first step, isn't it? No one is pushing to have this in
Newton. Even Ocata time frame seems like unrealistic.

-- 
Cheers,
Roman Dobosz