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<p class="MsoNormal"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif;color:#1F497D">Hi all.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif;color:#1F497D">This is the agent of today’s discussion.<o:p></o:p></span></p>
<p class="MsoNormal"><a name="_MailEndCompose"></a><a href="https://etherpad.openstack.org/p/cyborg-nova-poc"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">https://etherpad.openstack.org/p/cyborg-nova-poc</span></a><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif;color:#1F497D">BR<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif;color:#1F497D">Feng, Shaohe<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><a name="_____replyseparator"></a><b><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif"> Zhipeng Huang [mailto:zhipengh512@gmail.com]
<br>
<b>Sent:</b> 2018</span><span style="font-size:11.0pt">年</span><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif">3</span><span style="font-size:11.0pt">月</span><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif">8</span><span style="font-size:11.0pt">日</span><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif">
12:08<br>
<b>To:</b> Feng, Shaohe <shaohe.feng@intel.com><br>
<b>Cc:</b> openstack-dev@lists.openstack.org; openstack-operators@lists.openstack.org; Du, Dolpher <dolpher.du@intel.com>; Ding, Jian-feng <jian-feng.ding@intel.com>; Sun, Yih Leong <yih.leong.sun@intel.com>; Nadathur, Sundar <sundar.nadathur@intel.com>; Dutch
<dalthoff@xilinx.com>; Rushil Chugh <rushil.chugh@gmail.com>; Nguyen Hung Phuong <phuongnh@vn.fujitsu.com>; Justin Kilpatrick <jkilpatr@redhat.com>; Ranganathan, Shobha <shobha.ranganathan@intel.com>; zhuli <zhuli27@huawei.com>; bao.yumeng@zte.com.cn; Li Liu
<liliueecg@gmail.com>; xiaodongpan@tencent.com; kong.wei2@zte.com.cn; li.xiang2@zte.com.cn<br>
<b>Subject:</b> Re: [openstack-dev][cyborg][glance][nova]cyborg FPGA management flow disscusion.<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US">Thanks Shaohe,<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US">Let's schedule a video conf session next week. <o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US">On Thu, Mar 8, 2018 at 11:41 AM, Feng, Shaohe <<a href="mailto:shaohe.feng@intel.com" target="_blank">shaohe.feng@intel.com</a>> wrote:<o:p></o:p></span></p>
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<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif;color:#1F497D">Hi All:</span><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"><o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif;color:#1F497D"> </span><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"><o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif;color:#1F497D">The POC is here:</span><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"><o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Times New Roman",serif"><a href="https://github.com/shaohef/cyborg" target="_blank"><span style="font-family:"Calibri",sans-serif;color:#0563C1">https://github.com/shaohef/cyborg</span></a></span><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"><o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Times New Roman",serif;color:#1F497D"> </span><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"><o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><a name="m_-3565285586583357992__MailEndCompose"></a><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">BR<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">Shaohe Feng<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Times New Roman",serif;color:#1F497D"> </span><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"><o:p></o:p></span></p>
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<p class="MsoNormal"><a name="m_-3565285586583357992______replyseparat"></a><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif">_____________________________________________<br>
<b>From:</b> Feng, Shaohe <br>
<b>Sent:</b> 2018</span><span style="font-size:11.0pt">年</span><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif">2</span><span style="font-size:11.0pt">月</span><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif">12</span><span style="font-size:11.0pt">日</span><span lang="EN-US" style="font-size:11.0pt;font-family:"Calibri",sans-serif">
15:06<br>
<b>To:</b> <a href="mailto:openstack-dev@lists.openstack.org" target="_blank">openstack-dev@lists.openstack.org</a>;
<a href="mailto:openstack-operators@lists.openstack.org" target="_blank">openstack-operators@lists.openstack.org</a><br>
<b>Cc:</b> Du, Dolpher <<a href="mailto:dolpher.du@intel.com" target="_blank">dolpher.du@intel.com</a>>; Zhipeng Huang <<a href="mailto:zhipengh512@gmail.com" target="_blank">zhipengh512@gmail.com</a>>; Ding, Jian-feng <<a href="mailto:jian-feng.ding@intel.com" target="_blank">jian-feng.ding@intel.com</a>>;
Sun, Yih Leong <<a href="mailto:yih.leong.sun@intel.com" target="_blank">yih.leong.sun@intel.com</a>>; Nadathur, Sundar <<a href="mailto:sundar.nadathur@intel.com" target="_blank">sundar.nadathur@intel.com</a>>; Dutch <<a href="mailto:dalthoff@xilinx.com" target="_blank">dalthoff@xilinx.com</a>>;
Rushil Chugh <<a href="mailto:rushil.chugh@gmail.com" target="_blank">rushil.chugh@gmail.com</a>>; Nguyen Hung Phuong <<a href="mailto:phuongnh@vn.fujitsu.com" target="_blank">phuongnh@vn.fujitsu.com</a>>; Justin Kilpatrick <<a href="mailto:jkilpatr@redhat.com" target="_blank">jkilpatr@redhat.com</a>>;
Ranganathan, Shobha <<a href="mailto:shobha.ranganathan@intel.com" target="_blank">shobha.ranganathan@intel.com</a>>; zhuli <<a href="mailto:zhuli27@huawei.com" target="_blank">zhuli27@huawei.com</a>>;
<a href="mailto:bao.yumeng@zte.com.cn" target="_blank">bao.yumeng@zte.com.cn</a>;
<a href="mailto:xiaodongpan@tencent.com" target="_blank">xiaodongpan@tencent.com</a>;
<a href="mailto:kong.wei2@zte.com.cn" target="_blank">kong.wei2@zte.com.cn</a>; <a href="mailto:li.xiang2@zte.com.cn" target="_blank">
li.xiang2@zte.com.cn</a>; Feng, Shaohe <<a href="mailto:shaohe.feng@intel.com" target="_blank">shaohe.feng@intel.com</a>><br>
<b>Subject:</b> [openstack-dev][cyborg][glance][nova]cyborg FPGA management flow disscusion.</span><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"><o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:10.5pt;font-family:"Times New Roman",serif"> </span><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"><o:p></o:p></span></p>
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<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Times New Roman",serif"> </span><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"><o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">Now I am working on an FPGA management POC with Dolpher.
<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">We have finished some code, and have discussion with Li Liu and some cyborg developer guys.
<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> <o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">Here are some discussions:<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> <o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">image management<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">1. User should upload the FPGA image to glance and set the tags as follow:<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">There are two suggestions to upload an FPGA image.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">A. use raw glance api like:<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> $ openstack image create --file mypath/FPGA.img fpga.img<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> $ openstack image set --tag FPGA --property vendor=intel --property type=crypto 58b813db-1fb7-43ec-b85c-3b771c685d22<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> The image must have "FPGA" tag and accelerator type(such as type=crypto).<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">B. cyborg support a new api to upload a image.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> This API will wrap glance api and include the above steps, also make image record in it's local DB.
<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> <o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">2. Cyborg agent/conductor get the FPGA image info from glance.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">There are also two suggestions to get the FPGA image info.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">A. use raw glance api.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">Cyborg will get the images by FPGA tag and timestamp periodically and store them in it's local cache.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">It will use the images tags and properties to form placement taits and resource_class name.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">B. store the imformations when call cybort's new upload API.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> <o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">3. Image download.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">call glance image download API to local file. and make a corresponding md5 files for checksum.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> <o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">GAP in image management</span><span style="font-size:10.5pt">：</span><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"><o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">missing related glance image client in cyborg.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> <o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">resource report management for scheduler.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">1. Cyborg agent/conductor need synthesize all useful information from FPGA driver and image information.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">The traits will be like:<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">CUSTOM_FPGA, CUSTOM_ACCELERATOR_CRYPTO,<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">The resource_class will be like:<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">CUSTOM_FPGA_INTEL_PF, CUSTOM_FPGA_INTEL_VF<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">{"inventories":<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> "CUSTOM_FPGA_INTEL_PF": {<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> "allocation_ratio": 1.0,<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> "max_unit": 4,<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> "min_unit": 1,<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> "reserved": 0,<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> "step_size": 1,<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> "total": 4<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> }<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">}<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> <o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> <o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">Accelerator claim and release:<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">1. Cybort will support the releated API for accelerator claim and release.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">It can pass the follow parameters:<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> nodename: Which host that accelerator located on, it is required.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> type: This accelerator type, cyborg can get image uuid by it. it is optional.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> image uuid: the uuid of FPGA bitstream image, . it is optional.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> traits: the traits info that cyborg reports to placement.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> resource_class: the resource_class name that reports to placement.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">And return the address for the accelerator. At present, it is the PCIE_ADDRESS.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">2. When claim an accelerator, type and image is None, cybort will not program the fpga for user.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> <o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">FPGA accelerator program API:<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">We still need to support an independent program API for some specific scenarios.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">Such as as a FPGA developer, I will change my verilog logical frequently and need to do verification on
my guest.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">I upload my new bitstream image to glance, and call cyborg to program my FPGA accelerator.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> <o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">End user operations follow:<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">1. upload an bitstream image to glance if necessary and set its tags(at least FPGA is requied) and property.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> sucn as: --tag FPGA --property vendor=intel --property type=crypto<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">2. list the FPGA related traits and resource_class names by placement API.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> such as get "CUSTOM_FPGA_INTEL_PF" resource_class names and "CUSTOM_HW_INTEL,CUSTOM_HW_CRYPTO" traits.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">3. create a new falvor wiht his expected traits and resource_class as extra spec.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> such as:<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> "resourcesn:CUSTOM_FPGA_INTEL_PF=2" n is an integer or empty string.
<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> "required:CUSTOM_HW_INTEL,CUSTOM_HW_CRYPTO".<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">4. create the VM with this flavor.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> <o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"> <o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">BR<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif">Shaohe Feng<o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Times New Roman",serif"> </span><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"><o:p></o:p></span></p>
<p class="MsoNormal" style="text-align:justify;text-justify:inter-ideograph"><span lang="EN-US" style="font-size:10.5pt;font-family:"Times New Roman",serif"> </span><span lang="EN-US" style="font-size:10.5pt;font-family:"Calibri",sans-serif"><o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US"><br>
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<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US">-- <o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US">Zhipeng (Howard) Huang<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US">Standard Engineer<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US">IT Standard & Patent/IT Product Line<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US">Huawei Technologies Co,. Ltd<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US">Email: <a href="mailto:huangzhipeng@huawei.com" target="_blank">
huangzhipeng@huawei.com</a><o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US">Office: Huawei Industrial Base, Longgang, Shenzhen<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US">(Previous)<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US">Research Assistant<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US">Mobile Ad-Hoc Network Lab, Calit2<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US">University of California, Irvine<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US">Email: <a href="mailto:zhipengh@uci.edu" target="_blank">
zhipengh@uci.edu</a><o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US">Office: Calit2 Building Room 2402<o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span lang="EN-US">OpenStack, OPNFV, OpenDaylight, OpenCompute Aficionado<o:p></o:p></span></p>
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